1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more specifically to insulated gate field effect devices.
2. Description of the Prior Art
The performance of semi-conductor field effect devices has been greatly improved since the use of sidewall spacers on polycrystalline silicon gates has become common. The spacers allow formation of a lightly doped drain (LDD) region next to the channel region.
Such devices are formed by making a light phosphorus implant to form the lightly doped drain regions, followed by formation of sidewall oxide spacers on the sides of the polycrystalline silicon gate. These spacers are formed by depositing a conformal layer of oxide over the integrated circuit, and anisotropically etching this layer. Following sidewall spacer formation, heavily doped drain regions are formed by implanting arsenic. The sidewall spacers protect the lightly doped drain regions from the arsenic implant.
The formation of lightly doped drain regions is useful because doing so allows fabrication of small transistors that do not suffer from the "hot electron" effect. Smaller devices translate directly into a higher device packing density on the integrated circuit. This in turn translates to faster, less expensive circuits.
One disadvantage of LDD formation is the extra manufacturing steps involved. Even though both light and heavy drain doping are self-aligned, two separate implants of different materials must be made. The implants cannot be made without removing the wafer containing the integrated circuit from the implanter because the oxide sidewalls must be formed between implant steps. This adds some complexity to the process flow, and cost to the integrated circuit.
It would be desirable to provide a technique for forming lightly doped drain regions which is simpler than current processes. It is further desirable for such a technique to provide good device characteristics for the field effect transistors formed thereby.